1. Technical field
The embodiments herein generally relate to a memory device and particularly relate to Memristors based memory cells in designing integrated circuits (IC). The embodiments herein more particularly relates to a system and method for designing a hybrid memory cell with Memristor as memory element, and Complementary Metal-Oxide Semiconductor(CMOS) control logic for handling all peripheral circuits and input and output of data.
2. Description of the Related Art
The discovery of realizing a memristor as a physical device in 2008 spurred a great interest in using the memristors as a fundamental electronic element. The memristor based technology provides a much better scalability and a higher utilization, when used as a memory. Also, the memristor based technology provides a lower overall energy consumption compared to a traditional CMOS or Flash technology.
The memristor is made of a thin film of a semiconductor oxide. The memristor is an attractive option due to its smaller size starting at 10 nm, relatively low voltage requirements and non-volatile state. Another advantage of the memristor is its compatibility with the current CMOS process technology where the thin film can be realized with a minimum number of extra masks.
The memristors can play an important role in improving a scalability and an efficiency of an existing memory technology. The memristor is a two-terminal circuit element that operates in one of the two nonvolatile resistive states (on or off). These unique characteristics of the memristors give them an important role in shaping a future of the semiconductors as they hold many advantages over the transistors. The
Memristors consume much less power than the transistors as they do not require power to retain a state and they are leakage free. In addition to, the small size of a Memristor (<10 nm,) two terminals will improve the scalability of integrated circuits significantly.
The requirements for an embedded memory with a higher density and a lower power are increasing exponentially. This increase is driven by a high demand for a performance and low-power especially for the mobile systems which integrate a wide range of functionality, such as digital cameras, 3-D graphics, MP3 players, email, communication protocols, cryptography, and other applications. However, a technology scaling which enables a packing of 100's of millions of transistors on a same die brings many new design challenges due to an increase in a leakage and variability combined with the requirements for a low voltage supply operation.
The currently available main stream/CMOS-based memory technologies such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Flash, face many challenges in a pursuit to meet an increasing demand for a quick/faster processing and for a larger data size due to the scaling limitations both in terms of an area and a voltage. For instance, SRAM, the most reliable on-chip memory due to a fast access time, is reaching its physical limits in achieving the higher densities and lowering a power consumption. While DRAM which used as a main memory for its high density features also faces challenges due to a voltage scaling requiring an increased cell capacitance. The challenges in the Flash memory are in a cell to cell interface in closely packed cell and a stress-induced leakage current due to a programming with a high voltage across an ultra-thin oxide. In addition to the above, the progress in utilizing the other emerging magnetic-based memory technologies such as embedded Dynamic Random Access Memory (eDRAM), Magneto-Resistive Random Access Memory (MRAM), and Phase Change Random Access Memory (PCRAM), is hindered by a lack of compatibility with the CMOS devices, a slow access time, a temperature sensitivity and a limited scalability. A Phase Change Random Access Memory (PCRAM) has been investigated for long time but a requirement of high voltage to cause a phase change in PCRAM makes the PCRAM less attractive for the low power applications. There have been several attempts to realize a memristor-based memory.
According to one of the prior arts, an approach is provided to design a memristor-based memory as nano-wire crossbar arrays with a memristor at each cross-point (junction). Such a design faces many challenges as it is relatively new and it is not highly compatible with an existing fabrication technology. Also, the crossbar arrays were shown to suffer from the existence of sneak paths in which a stored data at one cross-point (junction) can be easily misread.
According to another prior art, a method to incorporate the memristors in a memory technology is disclosed. The method integrates the memristors within the existing CMOS based memory units. The approach proposed a design for a hybrid memristor-CMOS based Content Addressable Memory (CAM) cell. However, Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for such memory shows that the memristor state is not stable under a continuous reading. Also, a high level architecture for such memory was not designed.
According to another prior art, a SRAM-based memory unit is disclosed. The SRAM uses the traditional six transistors (6T cell SRAM) and is a dominant approach to build an embedded memory. The usage of SRAM adds to the traditional challenges like power, area, yield, timing etc., that are also present for logic gates. The memory unit makes up (occupies) more than sixty percent (60%) of modern processor or SOC and generates the challenges such as retention voltage, minimum voltage, leakage power etc . . . which are specific to a memory unit.
In addition to the 6T SRAM which faces the challenges listed above, the Embedded DRAM (eDRAM) has been proposed as an alternative to 6T SRAM. The eDRAM is found to be less attractive due to a slower access time, a need for refreshes, and an added cost due to additional masks needed to realize the added capacitor . Other Magnetic based memory like MRAM has also been investigated but its adaption has not been successful due to its bigger area and a limited scaling in addition to a slow access time.
Hence, there is a need for a method and a system to design an improved hybrid memory cell with the memristors and CMOS devices. Also, there is a need for a method and a system to design a CMOS logic for controlling a hybrid memory cell. Further, there is a need for a method and a system for integrating a hybrid memory cell with an existing technology and a memory array architecture. Still further, there is a need for a memory cell with a high density and low power consumption properties. Still further, there is a need for providing a specific solution to the problems in a memory cell of a System-on-Chip (SOC) integrated circuit (IC).
The abovementioned shortcomings, disadvantages and problems are addressed herein and which will be understood by reading and studying the following specification.